Typically, a liquid crystal display (LCD) panel includes a plurality of data lines and gate lines, the data lines being perpendicular to the gate lines. A plurality of pixel electrodes and a plurality of thin film transistors are formed in an active area in which the data lines and the gate lines typically cross each other at right angles.
The data lines and the gate lines typically extend out of the active area for applying signals from an integrated circuit driver. A plurality of pads are formed in an out-lead bonding (OLB) pad area near the periphery of the active area. The OLB pad area typically includes a pad block which is used for mounting the integrated circuit driver. The pad block is typically connected to a fan-out block having a plurality of leads formed to connect the gate lines or data lines to the integrated circuit driver at a plurality of bonding sites.
A conventional LCD panel is described in further detail with reference to FIGS. 1-3. As shown in FIG. 1, a conventional LCD panel includes a plurality of data lines 3 and gate lines 2 which cross each other at right angles on a display panel 1. The data 3 lines and the gate 2 lines cross each other in an active area B at which a plurality of pixel electrodes and thin film transistors are formed.
The data lines 3 and the gate lines 2 extend outside of the active area B for connection to integrated circuit drivers. A plurality of pads are formed in pad areas 4 near the periphery of the active area B. In order to connect the gate lines 2 and the data lines 3 to the pads in the pad areas 4, fan-out blocks 6 are formed in an OLB pad area C. The fan-out blocks 6 include a plurality of leads 5 formed so that the extended gate and data lines 2, 3 may be gathered for connection to the pads in the pad areas 4. As illustrated in FIG. 2, a typical fan-out block 6 includes a plurality of leads 5 which run in straight lines and have equal thickness and width.
The resistance of the lead in the conventional LCD may be calculated as follows: EQU R=.rho..times.L/S=(.rho..times.L)/(T.times.W),
where .rho., L, S, T and W represent resistivity, length of the lead, cross sectional area of the lead, thickness of the lead and width of the lead, respectively. The resistivity .rho. typically is a constant which is dependent on the material from which the lead is fabricated. If the thickness and width of the lead are constant throughout the lead length L, the resistance R varies in proportion to the length L.
According to the conventional configuration illustrated in FIGS. 1-2, the difference in resistance between leads 5 in the fan-out block 6 may generate time differences in signals being carried by the leads. Consequently, image quality of the display may be degraded due to time variation of the signals, especially in large-scale displays. For example, the difference of resistance between leads 5 of the fan-out block 6 connected to a plurality of gate lines 2 may cause a time difference in switching on thin film transistors of the LCD elements, potentially degrading image quality.